Analog VLSI neural network implementations of hardware annealing and winner-take-all functions

Joongho Choi, Bing J. Sheu, Sudhir M. Gowda

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The hardware annealing function plays a key role in searching for the optimal solutions for Hopfield neural networks and multi-layer back-propagation networks. The winner-take-all function is required in the operation of competitive-learning networks. Design and VLSI implementation of these two functions have been accomplished. Demonstration of hardware annealing with different synapse circuits is presented. The new high-speed analog winner-take-all circuit is linearly extendable to at least 1,024 inputs.

Original languageEnglish
Title of host publication1991 Proceedings of the 34th Midwest Symposium on Circuits and Systems, MWSCAS 1991
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages344-347
Number of pages4
ISBN (Electronic)0780306201
DOIs
StatePublished - 1991
Event34th Midwest Symposium on Circuits and Systems, MWSCAS 1991 - Monterey, United States
Duration: 14 May 199217 May 1992

Publication series

NameMidwest Symposium on Circuits and Systems
ISSN (Print)1548-3746

Conference

Conference34th Midwest Symposium on Circuits and Systems, MWSCAS 1991
Country/TerritoryUnited States
CityMonterey
Period14/05/9217/05/92

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