Analysis and optimization of RC delay in vertical nanoplate FET

In this paper, we have analyzed short channel effects (SCEs) and RC delay with Vertical nanoplate FET (VNFET) using 3-D Technology computer-aided design (TCAD) simulation. The device is based on International Technology Road-map for Semiconductor (ITRS) 2013 recommendations, and it has initially gate length (L_G) of 12.2 nm, channel thickness (T_ch) of 4 nm, and spacer length (L_SD) of 6 nm. To obtain improved performance by reducing RC delay, each dimension is adjusted (L_G = 12.2 nm, T_ch = 6 nm, L_SD = 11.9 nm). It has each characteristic in this dimension (I_on/I_off = 1.64 × 10⁵, Subthreshold swing (S.S.) = 73 mV/dec, Drain-induced barrier lowering (DIBL) = 60 mV/V, and RC delay = 0.214 ps). Furthermore, with long shallow trench isolation (STI) length and thick insulator thickness (T_i), we can reduce RC delay from 0.214 ps to 0.163 ps. It is about a 23.8% reduction. Without decreasing drain current, there is a reduction of RC delay as reducing outer fringing capacitance (C_of). Finally, when source/drain spacer length is set to be different, we have verified RC delay to be optimum.