TY - GEN
T1 - Analysis of self-heating effects in vertical MOSFETs according to device geometry
AU - Myeong, Ilho
AU - Son, Dokyun
AU - Kim, Hyunsuk
AU - Kang, Myounggon
AU - Shin, Hyungcheol
N1 - Publisher Copyright:
© 2017 JSAP.
PY - 2017/12/29
Y1 - 2017/12/29
N2 - In this paper, the Self-Heating Effects in Vertical FETs(VFET) have been investigated according to device geometry. It is demonstrated that the temperature of the device increases by using a low-k dielectric and an air gap between the metal lines. In addition, when air spacers are used, the lattice temperature is further increased and the on current reduction ratio increases compared to the common spacer. Also, to release the thermal bottleneck to the substrate side, the metal pad size was adjusted and the composition of the Shallow Trench Isolation (SII) was changed.
AB - In this paper, the Self-Heating Effects in Vertical FETs(VFET) have been investigated according to device geometry. It is demonstrated that the temperature of the device increases by using a low-k dielectric and an air gap between the metal lines. In addition, when air spacers are used, the lattice temperature is further increased and the on current reduction ratio increases compared to the common spacer. Also, to release the thermal bottleneck to the substrate side, the metal pad size was adjusted and the composition of the Shallow Trench Isolation (SII) was changed.
UR - http://www.scopus.com/inward/record.url?scp=85051015862&partnerID=8YFLogxK
U2 - 10.23919/SNW.2017.8242299
DO - 10.23919/SNW.2017.8242299
M3 - Conference contribution
AN - SCOPUS:85051015862
T3 - 2017 Silicon Nanoelectronics Workshop, SNW 2017
SP - 65
EP - 66
BT - 2017 Silicon Nanoelectronics Workshop, SNW 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd Silicon Nanoelectronics Workshop, SNW 2017
Y2 - 4 June 2017 through 5 June 2017
ER -