TY - GEN
T1 - Analysis on extension region in nanowire FET considering RC delay and electrical characteristics
AU - Kim, Jongsu
AU - Woo, Changbeom
AU - Kang, Myounggon
AU - Shin, Hyungcheol
N1 - Publisher Copyright:
© 2017 JSAP.
PY - 2017/12/29
Y1 - 2017/12/29
N2 - Device characteristics in the operating region, subthreshold region, and OFF region were analyzed to propose optimum design guideline for nanowire FET. First, the research was focused on the structure of extension region in perspective of RC delay. Also, Subthreshold Swing (SS) and Gate Induced Drain Leakage (GIDL) were investigated because these characteristics are greatly affected by the structure of the extension region. Therefore, by considering all characteristics in three regions of the device, it was found that the best characteristics were shown when the extension length was 6 nm without an overlap or with slight underlap.
AB - Device characteristics in the operating region, subthreshold region, and OFF region were analyzed to propose optimum design guideline for nanowire FET. First, the research was focused on the structure of extension region in perspective of RC delay. Also, Subthreshold Swing (SS) and Gate Induced Drain Leakage (GIDL) were investigated because these characteristics are greatly affected by the structure of the extension region. Therefore, by considering all characteristics in three regions of the device, it was found that the best characteristics were shown when the extension length was 6 nm without an overlap or with slight underlap.
UR - http://www.scopus.com/inward/record.url?scp=85051073176&partnerID=8YFLogxK
U2 - 10.23919/SNW.2017.8242288
DO - 10.23919/SNW.2017.8242288
M3 - Conference contribution
AN - SCOPUS:85051073176
T3 - 2017 Silicon Nanoelectronics Workshop, SNW 2017
SP - 43
EP - 44
BT - 2017 Silicon Nanoelectronics Workshop, SNW 2017
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 22nd Silicon Nanoelectronics Workshop, SNW 2017
Y2 - 4 June 2017 through 5 June 2017
ER -