TY - GEN
T1 - Analytic approach to power-constrained CMOS low-noise amplifier design with figure of merit consideration
AU - Song, Ickhyun
AU - Koo, Min Suk
AU - Jung, Hakchul
AU - Jhon, Hee Sauk
AU - Shin, Hyungcheol
PY - 2007
Y1 - 2007
N2 - In this paper, design approach for a 5.8-GHz power-constrained CMOS low-noise amplifier using 0.13-μm process technology is presented. To evaluate the overall performance of an LNA, figure of merit (FoM) is adopted. Figure of merit includes power gain, noise figure, power dissipation and the operation frequency. Each performance factor of FoM is analytically expressed in device parameters. We show that FoM is maximized by optimizing the transistor size and bias condition. Effect of the external capacitance between the gate and the source of the input transistor for power-constrained design is explained and its influence on FoM is also discussed.
AB - In this paper, design approach for a 5.8-GHz power-constrained CMOS low-noise amplifier using 0.13-μm process technology is presented. To evaluate the overall performance of an LNA, figure of merit (FoM) is adopted. Figure of merit includes power gain, noise figure, power dissipation and the operation frequency. Each performance factor of FoM is analytically expressed in device parameters. We show that FoM is maximized by optimizing the transistor size and bias condition. Effect of the external capacitance between the gate and the source of the input transistor for power-constrained design is explained and its influence on FoM is also discussed.
UR - http://www.scopus.com/inward/record.url?scp=48649087440&partnerID=8YFLogxK
U2 - 10.1109/TENCON.2007.4428796
DO - 10.1109/TENCON.2007.4428796
M3 - Conference contribution
AN - SCOPUS:48649087440
SN - 1424412722
SN - 9781424412723
T3 - IEEE Region 10 Annual International Conference, Proceedings/TENCON
BT - TENCON 2007 - 2007 IEEE Region 10 Conference
T2 - IEEE Region 10 Conference, TENCON 2007
Y2 - 30 October 2007 through 2 November 2007
ER -