TY - GEN
T1 - Automatic CUDA code synthesis framework for multicore CPU and GPU architectures
AU - Jung, Hanwoong
AU - Yi, Youngmin
AU - Ha, Soonhoi
PY - 2012
Y1 - 2012
N2 - Recently, general purpose GPU (GPGPU) programming has spread rapidly after CUDA was first introduced to write parallel programs in high-level languages for NVIDIA GPUs. While a GPU exploits data parallelism very effectively, task-level parallelism is exploited as a multi-threaded program on a multicore CPU. For such a heterogeneous platform that consists of a multicore CPU and GPU, we propose an automatic code synthesis framework that takes a process network model specification as input and generates a multithreaded CUDA code. With the model based specification, one can explicitly specify both function-level and loop-level parallelism in an application and explore the wide design space in mapping of function blocks and selecting the communication methods between CPU and GPU. The proposed technique is complementary to other high-level methods of CUDA programming.
AB - Recently, general purpose GPU (GPGPU) programming has spread rapidly after CUDA was first introduced to write parallel programs in high-level languages for NVIDIA GPUs. While a GPU exploits data parallelism very effectively, task-level parallelism is exploited as a multi-threaded program on a multicore CPU. For such a heterogeneous platform that consists of a multicore CPU and GPU, we propose an automatic code synthesis framework that takes a process network model specification as input and generates a multithreaded CUDA code. With the model based specification, one can explicitly specify both function-level and loop-level parallelism in an application and explore the wide design space in mapping of function blocks and selecting the communication methods between CPU and GPU. The proposed technique is complementary to other high-level methods of CUDA programming.
KW - CUDA
KW - GPGPU
KW - automatic code synthesis
KW - model-based design
UR - http://www.scopus.com/inward/record.url?scp=84865265129&partnerID=8YFLogxK
U2 - 10.1007/978-3-642-31464-3_59
DO - 10.1007/978-3-642-31464-3_59
M3 - Conference contribution
AN - SCOPUS:84865265129
SN - 9783642314636
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 579
EP - 588
BT - Parallel Processing and Applied Mathematics - 9th International Conference, PPAM 2011, Revised Selected Papers
T2 - 9th International Conference on Parallel Processing and Applied Mathematics, PPAM 2011
Y2 - 11 September 2011 through 14 September 2011
ER -