Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

Joo Yun Seo; Yoon Kim; Sang Ho Lee; Daewoong Kwon; Hee Do Na; Hyun Chul Sohn; Jong Ho Lee; Byung Gook Park

doi:10.1109/EDTM.2019.8731328

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

Joo Yun Seo, Yoon Kim, Sang Ho Lee, Daewoong Kwon, Hee Do Na, Hyun Chul Sohn, Jong Ho Lee, Byung Gook Park

School of Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this work, we fabricated channel stacked NAND flash memory of which feature size has been scaled down to 40 nm. Adopting HfO₂ as a charge trapping layer enables us to reduce the thickness of charge trapping layer due to its large trap density compared to that of Si₃N₄. Also, a new programming method is demonstrated to reduce the total program time.

Original language	English
Title of host publication	2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	315-317
Number of pages	3
ISBN (Electronic)	9781538665084
DOIs	https://doi.org/10.1109/EDTM.2019.8731328
State	Published - Mar 2019
Event	2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 - Singapore, Singapore Duration: 12 Mar 2019 → 15 Mar 2019

Publication series

Name	2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019

Conference

Conference	2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019
Country/Territory	Singapore
City	Singapore
Period	12/03/19 → 15/03/19

Keywords

3D NAND
Charge Trap Layer
High-κ
and program scheme

Access to Document

10.1109/EDTM.2019.8731328

Cite this

Seo, J. Y., Kim, Y., Lee, S. H., Kwon, D., Na, H. D., Sohn, H. C., Lee, J. H., & Park, B. G. (2019). Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability. In 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 (pp. 315-317). Article 8731328 (2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDTM.2019.8731328

@inproceedings{454742ed1a55455bb2e29eb867c790c3,

title = "Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability",

abstract = "In this work, we fabricated channel stacked NAND flash memory of which feature size has been scaled down to 40 nm. Adopting HfO2 as a charge trapping layer enables us to reduce the thickness of charge trapping layer due to its large trap density compared to that of Si3N4. Also, a new programming method is demonstrated to reduce the total program time.",

keywords = "3D NAND, Charge Trap Layer, High-κ, and program scheme",

author = "Seo, {Joo Yun} and Yoon Kim and Lee, {Sang Ho} and Daewoong Kwon and Na, {Hee Do} and Sohn, {Hyun Chul} and Lee, {Jong Ho} and Park, {Byung Gook}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019 ; Conference date: 12-03-2019 Through 15-03-2019",

year = "2019",

month = mar,

doi = "10.1109/EDTM.2019.8731328",

language = "English",

series = "2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "315--317",

booktitle = "2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019",

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}

Seo, JY, Kim, Y, Lee, SH, Kwon, D, Na, HD, Sohn, HC, Lee, JH & Park, BG 2019, Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability. in 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019., 8731328, 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019, Institute of Electrical and Electronics Engineers Inc., pp. 315-317, 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019, Singapore, Singapore, 12/03/19. https://doi.org/10.1109/EDTM.2019.8731328

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability. / Seo, Joo Yun; Kim, Yoon; Lee, Sang Ho et al.
2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 315-317 8731328 (2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Na, Hee Do

AU - Sohn, Hyun Chul

AU - Lee, Jong Ho

AU - Park, Byung Gook

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AB - In this work, we fabricated channel stacked NAND flash memory of which feature size has been scaled down to 40 nm. Adopting HfO2 as a charge trapping layer enables us to reduce the thickness of charge trapping layer due to its large trap density compared to that of Si3N4. Also, a new programming method is demonstrated to reduce the total program time.

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ER -

Seo JY, Kim Y, Lee SH, Kwon D, Na HD, Sohn HC et al. Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability. In 2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 315-317. 8731328. (2019 Electron Devices Technology and Manufacturing Conference, EDTM 2019). doi: 10.1109/EDTM.2019.8731328

Channel-Stacked NAND Flash Memory with High-κ Charge Trapping Layer for High Scalability

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