Channel-stacked NAND flash memory with layer selection by multi-level operation (LSM)

Wandong Kim, Joo Yun Seo, Yoon Kim, Se Hwan Park, Sang Ho Lee, Myung Hyun Baek, Jong Ho Lee, Byung Gook Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

8 Scopus citations

Abstract

In this paper, the channel stacked array (CSTAR) NAND flash memory with layer selection by multi-level operation (LSM) of string select transistor (SST) is proposed and investigated to solve problems of conventional channel stacked array. In case of LSM architecture, the stacked layers can be distinguished by combinations of multi-level states of SST and string select line (SSL) bias. Due to the layer selection performed by the bias of SSL, the placement of bit lines and word lines is similar to the conventional planar structure, and proposed CSTAR with LSM has no island-type SSLs. As a result of the advantages of the proposed architecture, various issues of conventional channel stacked NAND flash memory array can be solved.

Original languageEnglish
Title of host publication2013 IEEE International Electron Devices Meeting, IEDM 2013
Pages3.8.1-3.8.4
DOIs
StatePublished - 2013
Event2013 IEEE International Electron Devices Meeting, IEDM 2013 - Washington, DC, United States
Duration: 9 Dec 201311 Dec 2013

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)0163-1918

Conference

Conference2013 IEEE International Electron Devices Meeting, IEDM 2013
Country/TerritoryUnited States
CityWashington, DC
Period9/12/1311/12/13

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