Characteristics according to parameters of line edge roughness in ultra-scaled gate-all-around nanowire FET

Dokyun Son; Kyul Ko; Changbeom Woo; Myounggon Kang; Hyungcheol Shin

doi:10.1166/jnn.2017.14719

Characteristics according to parameters of line edge roughness in ultra-scaled gate-all-around nanowire FET

Dokyun Son, Kyul Ko, Changbeom Woo, Myounggon Kang, Hyungcheol Shin

School of Advanced Fusion Studies

Seoul National University

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

In this paper, behavior of variation induced by line edge roughness (LER) is investigated for 5 nm node gate-all-around (GAA) nanowire field effect transistors (NWFET) through 3-D technology computer-aided design (TCAD) simulations. The results are compared with 7 nm node FinFET to confirm the influence of LER according to the technology node. We found that LER critically aggravates device performance of a thin layer device by changing the channel thickness. Furthermore, the number of channel deformations induced by the LER plays an important role related with short channel effects (SCEs). Especially, 5 nm node nanowire FET has a very sensitive behavior due to a strong quantum effect (QE) and mobility degradation induced by thin layer, which has two times larger threshold voltage (V_th) variation than that of 7 nm node FinFET.

Original language	English
Pages (from-to)	7179-7182
Number of pages	4
Journal	Journal of Nanoscience and Nanotechnology
Volume	17
Issue number	10
DOIs	https://doi.org/10.1166/jnn.2017.14719
State	Published - Oct 2017

Keywords

Gate-All-Around (GAA) Nanowire Field Effect Transistors (NWFET)
Line Edge Roughness (LER)
Quantum Effect (QE)
Thin Layer
Variability

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10.1166/jnn.2017.14719

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title = "Characteristics according to parameters of line edge roughness in ultra-scaled gate-all-around nanowire FET",

abstract = "In this paper, behavior of variation induced by line edge roughness (LER) is investigated for 5 nm node gate-all-around (GAA) nanowire field effect transistors (NWFET) through 3-D technology computer-aided design (TCAD) simulations. The results are compared with 7 nm node FinFET to confirm the influence of LER according to the technology node. We found that LER critically aggravates device performance of a thin layer device by changing the channel thickness. Furthermore, the number of channel deformations induced by the LER plays an important role related with short channel effects (SCEs). Especially, 5 nm node nanowire FET has a very sensitive behavior due to a strong quantum effect (QE) and mobility degradation induced by thin layer, which has two times larger threshold voltage (Vth) variation than that of 7 nm node FinFET.",

keywords = "Gate-All-Around (GAA) Nanowire Field Effect Transistors (NWFET), Line Edge Roughness (LER), Quantum Effect (QE), Thin Layer, Variability",

author = "Dokyun Son and Kyul Ko and Changbeom Woo and Myounggon Kang and Hyungcheol Shin",

year = "2017",

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doi = "10.1166/jnn.2017.14719",

language = "English",

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AU - Son, Dokyun

AU - Ko, Kyul

AU - Woo, Changbeom

AU - Kang, Myounggon

AU - Shin, Hyungcheol

PY - 2017/10

Y1 - 2017/10

N2 - In this paper, behavior of variation induced by line edge roughness (LER) is investigated for 5 nm node gate-all-around (GAA) nanowire field effect transistors (NWFET) through 3-D technology computer-aided design (TCAD) simulations. The results are compared with 7 nm node FinFET to confirm the influence of LER according to the technology node. We found that LER critically aggravates device performance of a thin layer device by changing the channel thickness. Furthermore, the number of channel deformations induced by the LER plays an important role related with short channel effects (SCEs). Especially, 5 nm node nanowire FET has a very sensitive behavior due to a strong quantum effect (QE) and mobility degradation induced by thin layer, which has two times larger threshold voltage (Vth) variation than that of 7 nm node FinFET.

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Characteristics according to parameters of line edge roughness in ultra-scaled gate-all-around nanowire FET

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Keywords

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