Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

Jongwook Jeon; Myounggon Kang

doi:10.1109/TED.2016.2614275

Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

Jongwook Jeon, Myounggon Kang

School of Advanced Fusion Studies

Samsung

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with L_eff= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for fT , f MAX , and NF_min at 26 GHz up to 13%, 24%, and 18% compared with the reference layout scheme, respectively.

Original language	English
Article number	7588068
Pages (from-to)	4674-4677
Number of pages	4
Journal	IEEE Transactions on Electron Devices
Volume	63
Issue number	12
DOIs	https://doi.org/10.1109/TED.2016.2614275
State	Published - Dec 2016

Keywords

fMAX and NFmin
high frequency fT
Layout
RF CMOS

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10.1109/TED.2016.2614275

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title = "Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements",

abstract = "In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with Leff= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for fT , f MAX , and NFmin at 26 GHz up to 13%, 24%, and 18% compared with the reference layout scheme, respectively.",

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author = "Jongwook Jeon and Myounggon Kang",

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AU - Jeon, Jongwook

AU - Kang, Myounggon

PY - 2016/12

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N2 - In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with Leff= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for fT , f MAX , and NFmin at 26 GHz up to 13%, 24%, and 18% compared with the reference layout scheme, respectively.

AB - In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with Leff= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for fT , f MAX , and NFmin at 26 GHz up to 13%, 24%, and 18% compared with the reference layout scheme, respectively.

KW - fMAX and NFmin

KW - high frequency fT

KW - Layout

KW - RF CMOS

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JF - IEEE Transactions on Electron Devices

IS - 12

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ER -

Circuit Level Layout Optimization of MOS Transistor for RF and Noise Performance Improvements

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Keywords

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