Abstract
This study presents a compact model for three-dimensional (3D) NAND flash memory that incorporates ferroelectric properties to enable accurate circuit-level simulations. The model, implemented in Verilog-A, captures the saturation polarization-electric field (P-E) hysteresis behavior of a ferroelectric capacitor. To validate the model, simulation results are compared between TCAD and SPICE. Under identical programming conditions, the proposed oxide/nitride/ferroelectric (O/N/F) structure demonstrates approximately 3 V higher channel potential than the conventional oxide/nitride/oxide (O/N/O) structure, resulting in improved programming accuracy and cell stability. In addition, SPICE simulations run over an hour faster than TCAD, making the model efficient for circuit-level analysis.
| Original language | English |
|---|---|
| Pages (from-to) | 427-430 |
| Number of pages | 4 |
| Journal | IEEE Journal of the Electron Devices Society |
| Volume | 13 |
| DOIs | |
| State | Published - 2025 |
Keywords
- 3D NAND flash memory
- SPICE
- TCAD
- ferroelectric
- natural local self-boosting (NLSB)
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