Copper-silicon carbide composite plating for inhibiting the extrusion of through silicon via (TSV)

Se Ho Kee, Won Joong Kim, Jae Pil Jung

Research output: Contribution to journalArticlepeer-review

9 Scopus citations


For 3D packaging using TSV technology, it is required various techniques such as forming via holes on a wafer, filling conductive materials and interpretation of TSV reliability etc. Among them, solving the issue of reliability are standing out as a big problem for reaching commercialization in the future. When the conductive material filled in the TSV is expanded by the high-temperature process during the packaging process, it breaks the insulating layer and the metal interconnection which exist on via hole by extruding from the surface of the Si wafer. In this study, in order to suppress the Cu extrusion, electroplating was attempted by adding silicon carbide powder having almost no difference in thermal expansion coefficient with the Si chip in the Cu electroplating solution. As a result, the extrusion height of Cu-SiC was about 164 nm that is a height corresponding to 14.6% of the extrusion height of Cu. This is considered to be the result of extremely effectively suppressing the extrusion phenomenon after annealing by adding SiC powder with a low coefficient of thermal expansion into the conventional Cu plating solution.

Original languageEnglish
Pages (from-to)5-14
Number of pages10
JournalMicroelectronic Engineering
StatePublished - 1 Jun 2019


  • Composite plating
  • Extrusion
  • Packaging
  • Silicon carbide
  • Thermal expansion coefficient
  • Through-silicon-via


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