Current-Voltage Modeling of DRAM Cell Transistor Using Genetic Algorithm and Deep Learning

Jun Hui Park, Jung Nam Kim, Seonhaeng Lee, Gang Jun Kim, Namhyun Lee, Rock Hyun Baek, Dae Hwan Kim, Changhyun Kim, Myounggon Kang, Yoon Kim

Research output: Contribution to journalArticlepeer-review

Abstract

Accurate current-voltage (I-V) modeling based on the Berkeley short-channel insulated-gate field-effect transistor model (BSIM) is pivotal for integrated circuit simulation. However, the current BSIM model does not support a buried-channel-Array transistor (BCAT), which is the structure of the state-of-The-Art commercial dynamic random access memory (DRAM) cell transistor. In this work, we propose an intelligent I-V modeling technique that combines genetic algorithm (GA) and deep learning (DL). This hybrid technique facilitates both optimization of BSIM parameter and accurate I-V modeling, even for devices not originally supported by BSIM. Additionally, we extended application of the DL to model one of the principal degradation mechanisms of transistor, the hot-carrier degradation (HCD). The successful modeling results of I-V characteristic and device degradation demonstrated that devices not supported by BSIM can be accurately modeled for integrated circuit simulations.

Original languageEnglish
Pages (from-to)23881-23886
Number of pages6
JournalIEEE Access
Volume12
DOIs
StatePublished - 2024

Keywords

  • BCAT
  • BSIM-CMG
  • DRAM cell transistor
  • HCD
  • I-V modeling
  • compact modeling
  • deep learning
  • genetic algorithm

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