Design of 250 Mb/s 10-channel CMOS optical receiver array for computer communication

Kwangoh Kim, Jungryoul Choi, Joongho Choi

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

This paper describes design of 250 Mbps 10-channel CMOS optical receiver array for computer communication using the general-purpose CMOS technology. It is one of the most important building blocks for parallel optical interconnection system. The receiver array consists of the photo-detectors, amplifier chains and phase-locked loop for data recovery. The chip was fabricated in a 0.65 μm 2-poly, 2-metal CMOS technology and dissipates 330 mW for one-channel and 70 mW for PLL for ±2.5 v supply.

Original languageEnglish
Title of host publicationAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages29-32
Number of pages4
ISBN (Print)0780357051, 9780780357051
DOIs
StatePublished - 1999
Event1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
Duration: 23 Aug 199925 Aug 1999

Publication series

NameAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/TerritoryKorea, Republic of
CitySeoul
Period23/08/9925/08/99

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