TY - GEN
T1 - Design of 250 Mb/s 10-channel CMOS optical receiver array for computer communication
AU - Kim, Kwangoh
AU - Choi, Jungryoul
AU - Choi, Joongho
N1 - Publisher Copyright:
© 1999 IEEE.
PY - 1999
Y1 - 1999
N2 - This paper describes design of 250 Mbps 10-channel CMOS optical receiver array for computer communication using the general-purpose CMOS technology. It is one of the most important building blocks for parallel optical interconnection system. The receiver array consists of the photo-detectors, amplifier chains and phase-locked loop for data recovery. The chip was fabricated in a 0.65 μm 2-poly, 2-metal CMOS technology and dissipates 330 mW for one-channel and 70 mW for PLL for ±2.5 v supply.
AB - This paper describes design of 250 Mbps 10-channel CMOS optical receiver array for computer communication using the general-purpose CMOS technology. It is one of the most important building blocks for parallel optical interconnection system. The receiver array consists of the photo-detectors, amplifier chains and phase-locked loop for data recovery. The chip was fabricated in a 0.65 μm 2-poly, 2-metal CMOS technology and dissipates 330 mW for one-channel and 70 mW for PLL for ±2.5 v supply.
UR - http://www.scopus.com/inward/record.url?scp=39049085092&partnerID=8YFLogxK
U2 - 10.1109/APASIC.1999.824020
DO - 10.1109/APASIC.1999.824020
M3 - Conference contribution
AN - SCOPUS:39049085092
SN - 0780357051
SN - 9780780357051
T3 - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
SP - 29
EP - 32
BT - AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Y2 - 23 August 1999 through 25 August 1999
ER -