Design of a Capacitorless DRAM Based on a Polycrystalline-Silicon Dual-Gate MOSFET with a Fin-Shaped Structure

Hee Dae An, Sang Ho Lee, Jin Park, So Ra Min, Geon Uk Kim, Young Jun Yoon, Jae Hwa Seo, Min Su Cho, Jaewon Jang, Jin Hyuk Bae, Sin Hyung Lee, In Man Kang

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future.

Original languageEnglish
Article number3526
Issue number19
StatePublished - Oct 2022


  • 1T-DRAM
  • dual-gate
  • grain boundary
  • metal-oxide-semiconductor field-effect transistor
  • polycrystalline silicon
  • retention time
  • sensing margin


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