Design of capacitorless DRAM based on polycrystalline silicon nanotube structure

Jin Park; Min S.U. Cho; Sang H.O. Lee; Hee D.A.E. An; So R.A. Min; Geon U.K. Kim; Young J.U.N. Yoon; Jae H.W.A. Seo; Sin Hyung Lee; Jaewon Jang; Jin Hyuk Bae; In Man Kang

doi:10.1109/ACCESS.2021.3133572

Design of capacitorless DRAM based on polycrystalline silicon nanotube structure

Jin Park, Min S.U. Cho, Sang H.O. Lee, Hee D.A.E. An, So R.A. Min, Geon U.K. Kim, Young J.U.N. Yoon, Jae H.W.A. Seo, Sin Hyung Lee, Jaewon Jang, Jin Hyuk Bae, In Man Kang

School of Advanced Fusion Studies

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation.The proposed 1T-DRAM has the improved electrical performances because the outer gate (OG) and the inner gate (IG) effectively control the charges in the channel and body regions.IG has an asymmetric structure with an underlap (L_underlap) region to reduce the Shockley–Read–Hall (SRH) recombination rate.In the proposed 1T-DRAM, the write ‘‘1’’ operation is performed by band-to-band tunneling between the OG and the IG.The proposed 1T-DRAM cell exhibited a sensing margin of 422 µA/µm and a retention time of 120 ms at T = 358 K.

Original language	English
Pages (from-to)	163675-163685
Number of pages	11
Journal	IEEE Access
Volume	9
DOIs	https://doi.org/10.1109/ACCESS.2021.3133572
State	Published - 2021

Keywords

Dual-gate
Grain boundary
Metal–oxide–semiconductor field-effect transistor
Nanotube
One-transistor dynamic random-access memory
Polycrystalline silicon

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10.1109/ACCESS.2021.3133572

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title = "Design of capacitorless DRAM based on polycrystalline silicon nanotube structure",

abstract = "In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation.The proposed 1T-DRAM has the improved electrical performances because the outer gate (OG) and the inner gate (IG) effectively control the charges in the channel and body regions.IG has an asymmetric structure with an underlap (Lunderlap) region to reduce the Shockley–Read–Hall (SRH) recombination rate.In the proposed 1T-DRAM, the write {\textquoteleft}{\textquoteleft}1{\textquoteright}{\textquoteright} operation is performed by band-to-band tunneling between the OG and the IG.The proposed 1T-DRAM cell exhibited a sensing margin of 422 µA/µm and a retention time of 120 ms at T = 358 K.",

keywords = "Dual-gate, Grain boundary, Metal–oxide–semiconductor field-effect transistor, Nanotube, One-transistor dynamic random-access memory, Polycrystalline silicon",

author = "Jin Park and Cho, {Min S.U.} and Lee, {Sang H.O.} and An, {Hee D.A.E.} and Min, {So R.A.} and Kim, {Geon U.K.} and Yoon, {Young J.U.N.} and Seo, {Jae H.W.A.} and Lee, {Sin Hyung} and Jaewon Jang and Bae, {Jin Hyuk} and Kang, {In Man}",

year = "2021",

doi = "10.1109/ACCESS.2021.3133572",

language = "English",

volume = "9",

pages = "163675--163685",

journal = "IEEE Access",

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T1 - Design of capacitorless DRAM based on polycrystalline silicon nanotube structure

AU - Park, Jin

AU - Cho, Min S.U.

AU - Lee, Sang H.O.

AU - An, Hee D.A.E.

AU - Min, So R.A.

AU - Kim, Geon U.K.

AU - Yoon, Young J.U.N.

AU - Seo, Jae H.W.A.

AU - Lee, Sin Hyung

AU - Jang, Jaewon

AU - Bae, Jin Hyuk

AU - Kang, In Man

PY - 2021

Y1 - 2021

N2 - In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation.The proposed 1T-DRAM has the improved electrical performances because the outer gate (OG) and the inner gate (IG) effectively control the charges in the channel and body regions.IG has an asymmetric structure with an underlap (Lunderlap) region to reduce the Shockley–Read–Hall (SRH) recombination rate.In the proposed 1T-DRAM, the write ‘‘1’’ operation is performed by band-to-band tunneling between the OG and the IG.The proposed 1T-DRAM cell exhibited a sensing margin of 422 µA/µm and a retention time of 120 ms at T = 358 K.

AB - In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) based on a polycrystalline silicon nanotube structure with a grain boundary (GB) is designed and analyzed using technology computer-aided design (TCAD) simulation.The proposed 1T-DRAM has the improved electrical performances because the outer gate (OG) and the inner gate (IG) effectively control the charges in the channel and body regions.IG has an asymmetric structure with an underlap (Lunderlap) region to reduce the Shockley–Read–Hall (SRH) recombination rate.In the proposed 1T-DRAM, the write ‘‘1’’ operation is performed by band-to-band tunneling between the OG and the IG.The proposed 1T-DRAM cell exhibited a sensing margin of 422 µA/µm and a retention time of 120 ms at T = 358 K.

KW - Dual-gate

KW - Grain boundary

KW - Metal–oxide–semiconductor field-effect transistor

KW - Nanotube

KW - One-transistor dynamic random-access memory

KW - Polycrystalline silicon

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U2 - 10.1109/ACCESS.2021.3133572

DO - 10.1109/ACCESS.2021.3133572

M3 - Article

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SN - 2169-3536

VL - 9

SP - 163675

EP - 163685

JO - IEEE Access

JF - IEEE Access

ER -

Design of capacitorless DRAM based on polycrystalline silicon nanotube structure

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Keywords

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