Design of multi-time programmable memory for PMICs

In this paper, a multi-time programmable (MTP) cell based on a 0.18 Îm bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages â€" VPP (boosted voltage) and VNN (negative voltage) â€" is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG-SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG-SENSE transistor; only two p-wells are used â€" one for the TG-SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of 1 row × 64 columns and a user memory area of 3 rows × 64 columns, is newly proposed in this paper.