Device Investigation of Nanoplate Transistor with Spacer Materials

Hyungwoo Ko; Myounggon Kang; Jongwook Jeon; Hyungcheol Shin

doi:10.1109/TED.2018.2880966

Device Investigation of Nanoplate Transistor with Spacer Materials

Hyungwoo Ko, Myounggon Kang, Jongwook Jeon, Hyungcheol Shin

School of Advanced Fusion Studies

Research output: Contribution to journal › Article › peer-review

12 Scopus citations

Abstract

In this paper, a comparison of gate-all-around nanowire-FETs, nanoplate (NP)-FETs, and FinFETs was undertaken for the same areas of not only the gate metal but also the silicon channel, assuming the same conditions regarding the parasitic components. It is known that an NP-FET structure not only improves the delay performance but also enhances the immunity to short-channel effects. In addition, it is found that the use of a dual-k spacer with an NP-FET further improves the on-state as well as the off-state performances.

Original language	English
Article number	8556077
Pages (from-to)	766-770
Number of pages	5
Journal	IEEE Transactions on Electron Devices
Volume	66
Issue number	1
DOIs	https://doi.org/10.1109/TED.2018.2880966
State	Published - Jan 2019

Keywords

5-nm node
FinFET
gate all around (GAA)
nanoplate (NP)

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title = "Device Investigation of Nanoplate Transistor with Spacer Materials",

abstract = "In this paper, a comparison of gate-all-around nanowire-FETs, nanoplate (NP)-FETs, and FinFETs was undertaken for the same areas of not only the gate metal but also the silicon channel, assuming the same conditions regarding the parasitic components. It is known that an NP-FET structure not only improves the delay performance but also enhances the immunity to short-channel effects. In addition, it is found that the use of a dual-k spacer with an NP-FET further improves the on-state as well as the off-state performances.",

keywords = "5-nm node, FinFET, gate all around (GAA), nanoplate (NP)",

author = "Hyungwoo Ko and Myounggon Kang and Jongwook Jeon and Hyungcheol Shin",

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AB - In this paper, a comparison of gate-all-around nanowire-FETs, nanoplate (NP)-FETs, and FinFETs was undertaken for the same areas of not only the gate metal but also the silicon channel, assuming the same conditions regarding the parasitic components. It is known that an NP-FET structure not only improves the delay performance but also enhances the immunity to short-channel effects. In addition, it is found that the use of a dual-k spacer with an NP-FET further improves the on-state as well as the off-state performances.

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Device Investigation of Nanoplate Transistor with Spacer Materials

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