Abstract
A novel QPSK receiver is proposed that uses a four-port BPSK demodulator based on additive mixing, in conjunction with an LO phase shifter sequentially toggled between 0 (in-phase) and -π/2 (quadrature phase). Compared with conventional six-port demodulators, the proposed architecture has a 50 smaller circuit and lower power consumption in the frequency conversion. Furthermore, the proposed architecture can eliminate the need for a parallel-to-serial data converter in order to combine the I and Q data into serial data. The functionality of the proposed QPSK receiver is successfully demonstrated via the demodulation of the L-band QPSK signal at 10Mbit/s.
Original language | English |
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Pages (from-to) | 1244-1245 |
Number of pages | 2 |
Journal | Electronics Letters |
Volume | 45 |
Issue number | 24 |
DOIs | |
State | Published - 2009 |