Dynamic vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories

Ki Tae Park; Myounggon Kang; Soonwook Hwang; Youngsun Song; Jaewook Lee; Hansung Joo; Hyun Sil Oh; Jae Ho Kim; Yeong Taek Lee; Changhyun Kim; Wonseong Lee

Dynamic vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories

Ki Tae Park, Myounggon Kang, Soonwook Hwang, Youngsun Song, Jaewook Lee, Hansung Joo, Hyun Sil Oh, Jae Ho Kim, Yeong Taek Lee, Changhyun Kim, Wonseong Lee

School of Advanced Fusion Studies

Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

8 Scopus citations

Abstract

In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase cells are presented for achieving high program inhibition of sub-40nm MLC NAND flash and beyond. Compared to conventional method, over 40% program failure reduction after 30k P/E cycling was achieved in the proposed scheme. By optimizing erase Vth and its distribution using ISPP-after-erase, about 2 times better Vpass window margin was obtained in 40nm-node MLC NAND test chip.

Original language	English
Title of host publication	2009 Symposium on VLSI Circuits
Pages	24-25
Number of pages	2
State	Published - 2009
Event	2009 Symposium on VLSI Circuits - Kyoto, Japan Duration: 16 Jun 2009 → 18 Jun 2009

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2009 Symposium on VLSI Circuits
Country/Territory	Japan
City	Kyoto
Period	16/06/09 → 18/06/09

Cite this

@inproceedings{1cdfca6ec20c4461b89ca1b127fc4506,

title = "Dynamic vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories",

abstract = "In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase cells are presented for achieving high program inhibition of sub-40nm MLC NAND flash and beyond. Compared to conventional method, over 40% program failure reduction after 30k P/E cycling was achieved in the proposed scheme. By optimizing erase Vth and its distribution using ISPP-after-erase, about 2 times better Vpass window margin was obtained in 40nm-node MLC NAND test chip.",

author = "Park, {Ki Tae} and Myounggon Kang and Soonwook Hwang and Youngsun Song and Jaewook Lee and Hansung Joo and Oh, {Hyun Sil} and Kim, {Jae Ho} and Lee, {Yeong Taek} and Changhyun Kim and Wonseong Lee",

year = "2009",

language = "English",

isbn = "9784863480018",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "24--25",

booktitle = "2009 Symposium on VLSI Circuits",

note = "2009 Symposium on VLSI Circuits ; Conference date: 16-06-2009 Through 18-06-2009",

}

Park, KT, Kang, M, Hwang, S, Song, Y, Lee, J, Joo, H, Oh, HS, Kim, JH, Lee, YT, Kim, C & Lee, W 2009, Dynamic vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories. in 2009 Symposium on VLSI Circuits., 5205328, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. 24-25, 2009 Symposium on VLSI Circuits, Kyoto, Japan, 16/06/09.

Dynamic vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories. / Park, Ki Tae; Kang, Myounggon; Hwang, Soonwook et al.
2009 Symposium on VLSI Circuits. 2009. p. 24-25 5205328 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Dynamic vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories

AU - Park, Ki Tae

AU - Kang, Myounggon

AU - Hwang, Soonwook

AU - Song, Youngsun

AU - Lee, Jaewook

AU - Joo, Hansung

AU - Oh, Hyun Sil

AU - Kim, Jae Ho

AU - Lee, Yeong Taek

AU - Kim, Changhyun

AU - Lee, Wonseong

PY - 2009

Y1 - 2009

N2 - In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase cells are presented for achieving high program inhibition of sub-40nm MLC NAND flash and beyond. Compared to conventional method, over 40% program failure reduction after 30k P/E cycling was achieved in the proposed scheme. By optimizing erase Vth and its distribution using ISPP-after-erase, about 2 times better Vpass window margin was obtained in 40nm-node MLC NAND test chip.

AB - In this paper, dynamic Vpass ISPP schemes and optimizing Vth of erase cells are presented for achieving high program inhibition of sub-40nm MLC NAND flash and beyond. Compared to conventional method, over 40% program failure reduction after 30k P/E cycling was achieved in the proposed scheme. By optimizing erase Vth and its distribution using ISPP-after-erase, about 2 times better Vpass window margin was obtained in 40nm-node MLC NAND test chip.

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M3 - Conference contribution

AN - SCOPUS:70449372263

SN - 9784863480018

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - 24

EP - 25

BT - 2009 Symposium on VLSI Circuits

T2 - 2009 Symposium on VLSI Circuits

Y2 - 16 June 2009 through 18 June 2009

ER -

Dynamic vpass ISPP scheme and optimized erase Vth control for high program inhibition in MLC NAND flash memories

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