Effects of annealing on the electrical properties of the BLT/STA/Si structure for ferroelectric-gate field-effect transistors

We investigated the effects of annealing on the ferroelectric characteristics of (Bi,La)₄Ti₃O₁₂ (BLT) films deposited on Si(100) substrates with a 25-nm-thick SrTa₂O₆ (STA) buffer layer. The STA thin film annealed at 900°C for 3 minutes showed a 5.7-nm equivalent oxide thickness (EOT). The XRD analysis indicated that BLT films deposited on STA/Si structures had a polycrystalline phase with a preferred (117) orientation. The crystallinity was improved at higher temperatures. The capacitance-voltage (C-V) measurements revealed that the Au/BLT/STA/Si structures showed good ferroelectric properties and that the memory window width became larger as the annealing temperature was increased. For the BLT/STA/Si structures annealed at 750°C, the memory window width was about 1.5 V for a bias voltage sweep of ±5 V. The leakage current density was lower than 1 × 10^-7 A/cm² at 5 V. The data retention time of this structure was found to be longer than 15 hours.