TY - GEN
T1 - Effects of equivalent oxide thickness on bandgap-engineered SONOS flash memory
AU - Li, Dong Hua
AU - Park, Il Han
AU - Cho, Seongjae
AU - Yun, Jang Gn
AU - Lee, Jung Hoon
AU - Kim, Doo Hyun
AU - Lee, Gil Sung
AU - Kim, Yoon
AU - Park, Se Hwan
AU - Shim, Won Bo
AU - Kim, Wandong
AU - Park, Byung Gook
PY - 2009
Y1 - 2009
N2 - In order to implement more advanced nonvolatile memory device, many studies have been devoted to improve program/erase speed, endurance, and retention characteristics of nitride-based SONOS flash memory. As the CMOS device size shrinks down, the oxide-nitride-oxide (ONO) multi-layer where charge storage takes place in discrete traps in the silicon nitride layer needs the optimization of thickness and material properties in order for the SONOS flash device to follow the CMOS technology development trend. However, the retention characteristics of SONOS flash memory degrade with the scaling of tunnel oxide, although the program/erase speed is enhanced with the decrease of tunnel oxide thickness. To overcome this problem, we adopted the SONOS structures with bandgap-engineered tunnel oxide layer. The bandgap- engineered SONOS flash memory provides faster erase speed and better retention characteristics than the conventional SONOS flash memory in our previous work. In order to identify the limitation of the equivalent oxide thickness (EOT) of the ultra-thin ONO barrier which replaces the single tunnel oxide layer in the conventional SONOS structures, we have controlled the EOT of the ONO barrier by the standard CMOS process and investigated their effects on the program/erase speed, memory window, and data retention characteristics of the bandgap-engineered SONOS flash memory device. As a result, the experimental data show that the ONO has a degree of freedom in the thickness of each layer but the data retention loss should be still considered. The SONOS flash memory with bandgap engineering by adopting the ONO barrier instead of single tunnel oxide layer should have a lower limit of 3 nm as the EOT for both performance and reliability.
AB - In order to implement more advanced nonvolatile memory device, many studies have been devoted to improve program/erase speed, endurance, and retention characteristics of nitride-based SONOS flash memory. As the CMOS device size shrinks down, the oxide-nitride-oxide (ONO) multi-layer where charge storage takes place in discrete traps in the silicon nitride layer needs the optimization of thickness and material properties in order for the SONOS flash device to follow the CMOS technology development trend. However, the retention characteristics of SONOS flash memory degrade with the scaling of tunnel oxide, although the program/erase speed is enhanced with the decrease of tunnel oxide thickness. To overcome this problem, we adopted the SONOS structures with bandgap-engineered tunnel oxide layer. The bandgap- engineered SONOS flash memory provides faster erase speed and better retention characteristics than the conventional SONOS flash memory in our previous work. In order to identify the limitation of the equivalent oxide thickness (EOT) of the ultra-thin ONO barrier which replaces the single tunnel oxide layer in the conventional SONOS structures, we have controlled the EOT of the ONO barrier by the standard CMOS process and investigated their effects on the program/erase speed, memory window, and data retention characteristics of the bandgap-engineered SONOS flash memory device. As a result, the experimental data show that the ONO has a degree of freedom in the thickness of each layer but the data retention loss should be still considered. The SONOS flash memory with bandgap engineering by adopting the ONO barrier instead of single tunnel oxide layer should have a lower limit of 3 nm as the EOT for both performance and reliability.
UR - http://www.scopus.com/inward/record.url?scp=70449637701&partnerID=8YFLogxK
U2 - 10.1109/NMDC.2009.5167538
DO - 10.1109/NMDC.2009.5167538
M3 - Conference contribution
AN - SCOPUS:70449637701
SN - 9781424446964
T3 - 2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009
SP - 255
EP - 258
BT - 2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009
T2 - 2009 IEEE Nanotechnology Materials and Devices Conference, NMDC 2009
Y2 - 2 June 2009 through 5 June 2009
ER -