Efficient charge recovery logic

Yong Moon, Deog Kyoon Jeong

Research output: Contribution to conferencePaperpeer-review

19 Scopus citations


Efficient Charge Recovery Logic (ECRL) is proposed as a candidate for low-energy adiabatic logic. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows 4-6 times power reduction with a practical loading and operation frequency range. Circuits are designed using 1.0μm CMOS technology with a reduced threshold voltage of 0.2V.

Original languageEnglish
Number of pages2
StatePublished - 1995
EventProceedings of the 1995 Symposium on VLSI Circuits - Kyoto, Jpn
Duration: 8 Jun 199510 Jun 1995


ConferenceProceedings of the 1995 Symposium on VLSI Circuits
CityKyoto, Jpn


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