Efficient charge recovery logic

Yong Moon; Deog Kyoon Jeong

Efficient charge recovery logic

Yong Moon, Deog Kyoon Jeong

School of Electrical and Computer Engineering

Seoul National University

Research output: Contribution to conference › Paper › peer-review

19 Scopus citations

Abstract

Efficient Charge Recovery Logic (ECRL) is proposed as a candidate for low-energy adiabatic logic. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows 4-6 times power reduction with a practical loading and operation frequency range. Circuits are designed using 1.0μm CMOS technology with a reduced threshold voltage of 0.2V.

Original language	English
Pages	129-130
Number of pages	2
State	Published - 1995
Event	Proceedings of the 1995 Symposium on VLSI Circuits - Kyoto, Jpn Duration: 8 Jun 1995 → 10 Jun 1995

Conference

Conference	Proceedings of the 1995 Symposium on VLSI Circuits
City	Kyoto, Jpn
Period	8/06/95 → 10/06/95

Cite this

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title = "Efficient charge recovery logic",

abstract = "Efficient Charge Recovery Logic (ECRL) is proposed as a candidate for low-energy adiabatic logic. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows 4-6 times power reduction with a practical loading and operation frequency range. Circuits are designed using 1.0μm CMOS technology with a reduced threshold voltage of 0.2V.",

author = "Yong Moon and Jeong, {Deog Kyoon}",

year = "1995",

language = "English",

pages = "129--130",

note = "Proceedings of the 1995 Symposium on VLSI Circuits ; Conference date: 08-06-1995 Through 10-06-1995",

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TY - CONF

T1 - Efficient charge recovery logic

AU - Moon, Yong

AU - Jeong, Deog Kyoon

PY - 1995

Y1 - 1995

N2 - Efficient Charge Recovery Logic (ECRL) is proposed as a candidate for low-energy adiabatic logic. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows 4-6 times power reduction with a practical loading and operation frequency range. Circuits are designed using 1.0μm CMOS technology with a reduced threshold voltage of 0.2V.

AB - Efficient Charge Recovery Logic (ECRL) is proposed as a candidate for low-energy adiabatic logic. Power comparison with other logic circuits is performed on an inverter chain and a carry lookahead adder (CLA). ECRL CLA is designed as a pipelined structure for obtaining the same throughput as a conventional static CMOS CLA. Proposed logic shows 4-6 times power reduction with a practical loading and operation frequency range. Circuits are designed using 1.0μm CMOS technology with a reduced threshold voltage of 0.2V.

UR - http://www.scopus.com/inward/record.url?scp=0029508923&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0029508923

SP - 129

EP - 130

T2 - Proceedings of the 1995 Symposium on VLSI Circuits

Y2 - 8 June 1995 through 10 June 1995

ER -

Efficient charge recovery logic

Abstract

Conference

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