Flash ETOX virtual ground architecture: A future scaling direction

R. Koval, V. Bhachawat, C. Chang, M. Hajra, D. Kencke, Y. Kim, C. Kuo, T. Parent, M. Wei, B. J. Woo, A. Fazio

Research output: Contribution to journalConference articlepeer-review

11 Scopus citations


A 65nm generation virtual ground (VG) ETOX flash memory process capable of MLC operation and relying on a conventional channel hot electron program and F-N tunneling channel erase has been demonstrated. Several key process elements were successfully integrated to achieve functional test structures with 0.0315 μm2 cell size. The significant area scaling benefit was achieved in large part by replacing the drain contacts and metal interconnect in the array with a buried bitline diffusion implant. In addition to achieving the significant reduction in cell size, such an approach offers several important technological advantages compared to the conventional approach used by its predecessor technology and provides a promising path for continued future scaling of flash memories.

Original languageEnglish
Article number1469268
Pages (from-to)204-205
Number of pages2
JournalDigest of Technical Papers - Symposium on VLSI Technology
StatePublished - 2005
Event2005 Symposium on VLSI Technology - Kyoto, Japan
Duration: 14 Jun 200514 Jun 2005


  • ETOX™
  • Flash
  • Virtual ground


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