Flexible bottom-gate graphene transistors on Parylene C substrate and the effect of current annealing

Dong Wook Park, Hyungsoo Kim, Jihye Bong, Solomon Mikael, Tong June Kim, Justin C. Williams, Zhenqiang Ma

Research output: Contribution to journalArticlepeer-review

8 Scopus citations


Flexible graphene transistors built on a biocompatible Parylene C substrate would enable active circuitry to be integrated into flexible implantable biomedical devices. An annealing method to improve the performance of a flexible transistor without damaging the flexible substrate is also desirable. Here, we present a fabrication method of a flexible graphene transistor with a bottom-gate coplanar structure on a Parylene C substrate. Also, a current annealing method and its effect on the device performance have been studied. The localized heat generated by the current annealing method improves the drain current, which is attributed to the decreased contact resistance between graphene and S/D electrodes. A maximum current annealing power in the Parylene C-based graphene transistor has been extracted to provide a guideline for an appropriate current annealing. The fabricated flexible graphene transistor shows a field-effect mobility, maximum transconductance, and a Ion/Ioff ratio of 533.5 cm2/V s, 58.1 μS, and 1.76, respectively. The low temperature process and the current annealing method presented here would be useful to fabricate two-dimensional materials-based flexible electronics.

Original languageEnglish
Article number152105
JournalApplied Physics Letters
Issue number15
StatePublished - 10 Oct 2016


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