Fringe capacitance modeling in nanoplate mosfet using conformal mapping

Jongsu Kim, Myounggon Kang, Jongwook Jeon, Hyungcheol Shin

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

In this brief, the conformal mapping was used to model the fringe capacitance in a nanoplate FET. The proposed model is more accurate than the use of a previous model compared to simulation results, because it considers the range and shape of a potential formation, as well as the length and the location of extension. The gate metal of a circular channel has a different width depending on its height. Therefore, the total fringe capacitance of the circular channel is expressed by multiplying the fringe capacitance, as noted according to the height of the gate metal and the width corresponding to each height. Finally, we evaluate our model for various geometries which showed good agreement with 3-D TCAD simulation results.

Original languageEnglish
Article number8671499
Pages (from-to)2446-2449
Number of pages4
JournalIEEE Transactions on Electron Devices
Volume66
Issue number5
DOIs
StatePublished - May 2019

Keywords

  • Conformal mapping
  • fringe capacitance
  • nanoplate FET
  • parasitic capacitance

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