Gated twin-bit silicon-oxide-nitride-oxide-silicon NAND flash memory for high-density nonvolatile memory

Yoon Kim; Won Bo Shim; Byung Gook Park

doi:10.7567/JJAP.54.064201

Gated twin-bit silicon-oxide-nitride-oxide-silicon NAND flash memory for high-density nonvolatile memory

Yoon Kim, Won Bo Shim, Byung Gook Park

School of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

2 Scopus citations

Abstract

In this paper, we report the fabrication and analysis of the gated twin-bit NAND flash memory with a nitride charge-trapping layer. This device is based on the recessed channel structure, and it has an additional cut-off gate that enables 2-bit operation. Therefore, the density of the array can be doubled without any difficulty in patterning. The fabrication method for gated twin-bit (GTB) silicon-oxide-nitride-oxide-silicon (SONOS) memories and their electrical characteristics are described in this paper. Program/erase characteristics are observed and the 2-bit operation is verified by the forward-reverse reading scheme.

Original language	English
Article number	064201
Journal	Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume	54
Issue number	6
DOIs	https://doi.org/10.7567/JJAP.54.064201
State	Published - 1 Jun 2015

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title = "Gated twin-bit silicon-oxide-nitride-oxide-silicon NAND flash memory for high-density nonvolatile memory",

abstract = "In this paper, we report the fabrication and analysis of the gated twin-bit NAND flash memory with a nitride charge-trapping layer. This device is based on the recessed channel structure, and it has an additional cut-off gate that enables 2-bit operation. Therefore, the density of the array can be doubled without any difficulty in patterning. The fabrication method for gated twin-bit (GTB) silicon-oxide-nitride-oxide-silicon (SONOS) memories and their electrical characteristics are described in this paper. Program/erase characteristics are observed and the 2-bit operation is verified by the forward-reverse reading scheme.",

author = "Yoon Kim and Shim, {Won Bo} and Park, {Byung Gook}",

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N2 - In this paper, we report the fabrication and analysis of the gated twin-bit NAND flash memory with a nitride charge-trapping layer. This device is based on the recessed channel structure, and it has an additional cut-off gate that enables 2-bit operation. Therefore, the density of the array can be doubled without any difficulty in patterning. The fabrication method for gated twin-bit (GTB) silicon-oxide-nitride-oxide-silicon (SONOS) memories and their electrical characteristics are described in this paper. Program/erase characteristics are observed and the 2-bit operation is verified by the forward-reverse reading scheme.

AB - In this paper, we report the fabrication and analysis of the gated twin-bit NAND flash memory with a nitride charge-trapping layer. This device is based on the recessed channel structure, and it has an additional cut-off gate that enables 2-bit operation. Therefore, the density of the array can be doubled without any difficulty in patterning. The fabrication method for gated twin-bit (GTB) silicon-oxide-nitride-oxide-silicon (SONOS) memories and their electrical characteristics are described in this paper. Program/erase characteristics are observed and the 2-bit operation is verified by the forward-reverse reading scheme.

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Gated twin-bit silicon-oxide-nitride-oxide-silicon NAND flash memory for high-density nonvolatile memory

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