High speed ATM switch with common parallel buffers

We introduce a high speed N × N ATM switch in which the common buffer block is separated into M common parallel buffers (CPB). Each CPB can be operated at the same access speed as the interface rate by managing the address buffers so that there are no contentions to access the same CPB during cell input/output operations. We derive an analytical upper bound of cell loss probability (CLP) and then evaluate this system in terms of the CLP. The result shows that we can achieve much lower cell loss probability as we separate the memory into more CPBs. In case of 2N CPBs, we can obtain the low cell loss probability which is comparable to those of the conventional common buffer type switches.