High speed Cu filling into tapered TSV for 3-dimensional Si chip stacking

In Rak Kim, Sung Chul Hong, Jae Pil Jung

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13 Scopus citations


High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37μm at the via opening, and 32μm at the via bottom, respectively and a depth of 70 μn. SiO2, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was field to 100% at -5.85 mA/cm2 for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to ful the TSV in a short time.

Original languageEnglish
Pages (from-to)388-394
Number of pages7
JournalJournal of Korean Institute of Metals and Materials
Issue number5
StatePublished - May 2011


  • Defects
  • Electronic materials
  • Plating
  • Scanning electron microscopy (SEM)
  • Three dimensional packaging


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