TY - GEN
T1 - Highly scalable vertical bandgap-engineered NAND flash memory
AU - Cho, Seongjae
AU - Kim, Yoon
AU - Shim, Won Bo
AU - Li, Dong Hua
AU - Lee, Jong Ho
AU - Shin, Hyungcheol
AU - Park, Byung Gook
PY - 2010
Y1 - 2010
N2 - In this work, highly scalable charge trap flash (CTF) memory with bandgap-engineered storage node and vertical channel is proposed. Due to the compact cell layout without individual junction contacts, NAND flash memory has the most suitable architecture for mobile data storage media. In other to achieve even higher integration density, two NAND flash memory cells in the conventional sting are put together to have a common vertical channel as shown in Fig. l(a). The biggest merit in this array feature is that half-level reduction in foot-print can be achieved by using the sidewall control gates as shown in Fig. 1(b). Due to the vertical channel, the channel length can be simply controlled by anisotropic dry etch, which suppresses short channel effects (SCEs) effectively and enlarges the sensing margin. Fig. l(c) shows the schematic view of the array with circuit symbols. Also, in this novel flash memory, the memory storage node uses a bandgap-engineered (BE) multi-layer, where the oxide-nitride-oxide triple-layer replaces the tunnel oxide to improve the performances in operations [1-3]. The process architecture for fabricating the vertical BE-NAND flash memory is summarized in Fig. 2. The fin structures in both bitline (BL) and wordline (WL) directions have been formed by sidewall spacer patterning [4]. Among the several possible combinations of materials [5-6], nitride (Si3N4) and TEOS are used for the sidewall spacer and the supporting dummy pattern, respectively. Fig. 3 and 4 shows the process flow for Si fm constructions in both directions. After the fm consisted of Si-STI alternating pillars is formed in the WL direction, ONONO (20/20/20160160 Å) multi-layer is deposited. All the oxide layers were deposited by medium temperature oxidation (MTO) in an ambient of N2 160 sccm and DCS 40 sccm. The tunneling and storage nitride layers were deposited by LPCVD in the ambient of NH3 30 sccmIDCS 10 sccm/750 °C and NH3 100 sccm/DCS 30 sccm/785 °C, respectively. Subsequently, physically separated sidewall control gates used as WLs are formed by etch-back process. Fig. 5(a) through (c) show the images for fin structures and top view of the vertical BENAND flash with independent sidewall gates. After ILD/CMP/metallizationialloy, the fabrication is completed.
AB - In this work, highly scalable charge trap flash (CTF) memory with bandgap-engineered storage node and vertical channel is proposed. Due to the compact cell layout without individual junction contacts, NAND flash memory has the most suitable architecture for mobile data storage media. In other to achieve even higher integration density, two NAND flash memory cells in the conventional sting are put together to have a common vertical channel as shown in Fig. l(a). The biggest merit in this array feature is that half-level reduction in foot-print can be achieved by using the sidewall control gates as shown in Fig. 1(b). Due to the vertical channel, the channel length can be simply controlled by anisotropic dry etch, which suppresses short channel effects (SCEs) effectively and enlarges the sensing margin. Fig. l(c) shows the schematic view of the array with circuit symbols. Also, in this novel flash memory, the memory storage node uses a bandgap-engineered (BE) multi-layer, where the oxide-nitride-oxide triple-layer replaces the tunnel oxide to improve the performances in operations [1-3]. The process architecture for fabricating the vertical BE-NAND flash memory is summarized in Fig. 2. The fin structures in both bitline (BL) and wordline (WL) directions have been formed by sidewall spacer patterning [4]. Among the several possible combinations of materials [5-6], nitride (Si3N4) and TEOS are used for the sidewall spacer and the supporting dummy pattern, respectively. Fig. 3 and 4 shows the process flow for Si fm constructions in both directions. After the fm consisted of Si-STI alternating pillars is formed in the WL direction, ONONO (20/20/20160160 Å) multi-layer is deposited. All the oxide layers were deposited by medium temperature oxidation (MTO) in an ambient of N2 160 sccm and DCS 40 sccm. The tunneling and storage nitride layers were deposited by LPCVD in the ambient of NH3 30 sccmIDCS 10 sccm/750 °C and NH3 100 sccm/DCS 30 sccm/785 °C, respectively. Subsequently, physically separated sidewall control gates used as WLs are formed by etch-back process. Fig. 5(a) through (c) show the images for fin structures and top view of the vertical BENAND flash with independent sidewall gates. After ILD/CMP/metallizationialloy, the fabrication is completed.
UR - http://www.scopus.com/inward/record.url?scp=77957583817&partnerID=8YFLogxK
U2 - 10.1109/DRC.2010.5551967
DO - 10.1109/DRC.2010.5551967
M3 - Conference contribution
AN - SCOPUS:77957583817
SN - 9781424478705
T3 - Device Research Conference - Conference Digest, DRC
SP - 265
EP - 266
BT - 68th Device Research Conference, DRC 2010
T2 - 68th Device Research Conference, DRC 2010
Y2 - 21 June 2010 through 23 June 2010
ER -