Impact Ionization and Hot-Carrier Degradation in Saddle-Fin and Buried-Gate Transistor of Dynamic Random Access Memory at Cryogenic Temperature

Jun Park; Namhyun Lee; Gang Jun Kim; Hyun Seok Choi; Dae Hwan Kim; Changhyun Kim; Myounggon Kang; Yoon Kim

doi:10.1109/LED.2021.3067109

Impact Ionization and Hot-Carrier Degradation in Saddle-Fin and Buried-Gate Transistor of Dynamic Random Access Memory at Cryogenic Temperature

Jun Park, Namhyun Lee, Gang Jun Kim, Hyun Seok Choi, Dae Hwan Kim, Changhyun Kim, Myounggon Kang, Yoon Kim

Research output: Contribution to journal › Article › peer-review

5 Scopus citations

Abstract

Impact ionization and hot-carrier degradation (HCD) in buried-channel-array transistors (BCATs), which are used as the cell transistor, were investigated using sub-30 nm DRAM technology. The impact ionization rate was calculated by measuring the substrate current at different measurement conditions and modeled using an energy-driven model, which is suitable for short-channel transistors. In addition, HCD in BCAT under various operation conditions was analyzed. A multitrap-based approach, in which both interface- and oxide-trap generation were considered, was used to fit the experimental results. Our analysis and modeling results are useful in understanding and predicting the reliability of dynamic random access memory.

Original language	English
Article number	9393379
Pages (from-to)	653-656
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	42
Issue number	5
DOIs	https://doi.org/10.1109/LED.2021.3067109
State	Published - May 2021

Keywords

DRAM cell transistor
DRAM reliability
Hot-carrier degradation
buried-channel-array transistor
cryogenic computing system
impact ionization

Access to Document

10.1109/LED.2021.3067109

Cite this

@article{4eef7c319e384402b6d61e81394ef5df,

title = "Impact Ionization and Hot-Carrier Degradation in Saddle-Fin and Buried-Gate Transistor of Dynamic Random Access Memory at Cryogenic Temperature",

abstract = "Impact ionization and hot-carrier degradation (HCD) in buried-channel-array transistors (BCATs), which are used as the cell transistor, were investigated using sub-30 nm DRAM technology. The impact ionization rate was calculated by measuring the substrate current at different measurement conditions and modeled using an energy-driven model, which is suitable for short-channel transistors. In addition, HCD in BCAT under various operation conditions was analyzed. A multitrap-based approach, in which both interface- and oxide-trap generation were considered, was used to fit the experimental results. Our analysis and modeling results are useful in understanding and predicting the reliability of dynamic random access memory.",

keywords = "DRAM cell transistor, DRAM reliability, Hot-carrier degradation, buried-channel-array transistor, cryogenic computing system, impact ionization",

author = "Jun Park and Namhyun Lee and Kim, {Gang Jun} and Choi, {Hyun Seok} and Kim, {Dae Hwan} and Changhyun Kim and Myounggon Kang and Yoon Kim",

note = "Publisher Copyright: {\textcopyright} 1980-2012 IEEE.",

year = "2021",

month = may,

doi = "10.1109/LED.2021.3067109",

language = "English",

volume = "42",

pages = "653--656",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "5",

}

TY - JOUR

T1 - Impact Ionization and Hot-Carrier Degradation in Saddle-Fin and Buried-Gate Transistor of Dynamic Random Access Memory at Cryogenic Temperature

AU - Park, Jun

AU - Lee, Namhyun

AU - Kim, Gang Jun

AU - Choi, Hyun Seok

AU - Kim, Dae Hwan

AU - Kim, Changhyun

AU - Kang, Myounggon

AU - Kim, Yoon

PY - 2021/5

Y1 - 2021/5

N2 - Impact ionization and hot-carrier degradation (HCD) in buried-channel-array transistors (BCATs), which are used as the cell transistor, were investigated using sub-30 nm DRAM technology. The impact ionization rate was calculated by measuring the substrate current at different measurement conditions and modeled using an energy-driven model, which is suitable for short-channel transistors. In addition, HCD in BCAT under various operation conditions was analyzed. A multitrap-based approach, in which both interface- and oxide-trap generation were considered, was used to fit the experimental results. Our analysis and modeling results are useful in understanding and predicting the reliability of dynamic random access memory.

AB - Impact ionization and hot-carrier degradation (HCD) in buried-channel-array transistors (BCATs), which are used as the cell transistor, were investigated using sub-30 nm DRAM technology. The impact ionization rate was calculated by measuring the substrate current at different measurement conditions and modeled using an energy-driven model, which is suitable for short-channel transistors. In addition, HCD in BCAT under various operation conditions was analyzed. A multitrap-based approach, in which both interface- and oxide-trap generation were considered, was used to fit the experimental results. Our analysis and modeling results are useful in understanding and predicting the reliability of dynamic random access memory.

KW - DRAM cell transistor

KW - DRAM reliability

KW - Hot-carrier degradation

KW - buried-channel-array transistor

KW - cryogenic computing system

KW - impact ionization

UR - http://www.scopus.com/inward/record.url?scp=85103760558&partnerID=8YFLogxK

U2 - 10.1109/LED.2021.3067109

DO - 10.1109/LED.2021.3067109

M3 - Article

AN - SCOPUS:85103760558

SN - 0741-3106

VL - 42

SP - 653

EP - 656

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 5

M1 - 9393379

ER -

Impact Ionization and Hot-Carrier Degradation in Saddle-Fin and Buried-Gate Transistor of Dynamic Random Access Memory at Cryogenic Temperature

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this