Impact of sidewall spacer materials and gate underlap length on negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET)

In this study, a negative capacitance double-gate tunnel field-effect transistor (NCDG-TFET) with sidewall spacer engineering is proposed and its electrical characteristics are examined by technology computer-aided design (TCAD) simulation for lower subthreshold swing (SS) and higher on–off current ratio (I_on/I_off) than conventional planar TFET. In detail, the dielectric constant (κ) and length of sidewall spacer (L_spc) which determine gate-to-source/drain underlap are optimized for an enhanced device performance. The simulation study shows that the sidewall spacers at source and drain underlap need to be designed differently for high I_on and low ambipolar current (I_amb). In case of source underlap, the HfO₂ 3 nm-L_spc can enhance outer fringing field and I_on. On the other hand, the SiO₂ 15 nm-L_spc at drain underlap can alleviate I_amb due to low outer fringing field. As a result, the asymmetric structure shows ∼ 1.5 times larger I_on and ∼ 4 orders lower I_amb with smaller SS and turn-on voltage (V_on) than the conventional NCDG-TFET without sidewall spacer.