Impact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor

A symmetric tunnelfield-effect transistor (S-TFET) was recently proposed as an alternative device to address power density issues, featuring steep switching characteristic and bi-directional currentflow with its symmetric structure. Because 193-nm immersion lithography is paired up with double or multiple patterning techniques for further enhancement of patterning resolution, the effect of double-patterning and double-etching (2P2E)-induced gate line-edge roughness (LER) [versussingle-patterning and single-etching (1P1E)] on the S-TFET is investigated with various device design parameters. Finally, an investigation is conducted on the physical reasons which give rise to the difference in the LER parameters for 2P2E and 1P1E technique.