Abstract
Two new NAND structures using double common source line (CSL) and dummy switch and their read operation schemes as a solution for NAND flash memories have been proposed. Compared with conventional scheme, the proposed read schemes improves read disturb characteristicsbeyond sub-30nm technology node. By using proposed read scheme, the number of fail bits of proposed NAND was decreased than those ofconventional NAND at read cycles. Also, it was proven that they contribute to improve the performance and suppress the power consumption. The proposed NAND was verified by both simulation and experimental measurements in a fabricated 40nm multi level cell (MLC) NAND device.
Original language | English |
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Article number | 04DD03 |
Journal | Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers |
Volume | 50 |
Issue number | 4 PART 2 |
DOIs | |
State | Published - Apr 2011 |