Incremental redundancy to reduce data retention errors in flash-based SSDs

Heejin Park, Jaeho Kim, Jongmoo Choi, Donghee Lee, Sam H. Noh

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

28 Scopus citations

Abstract

As the market becomes competitive, SSD manufacturers are making use of multi-bit cell flash memory such as MLC and TLC chips in their SSDs. However, these chips have lower data retention period and endurance than SLC chips. With the reduced data retention period and endurance level, retention errors occur more frequently. One solution for these retention errors is to employ strong ECC to increase error correction strength. However, employing strong ECC may result in waste of resources during the early stages of flash memory lifetime as it has high reliability and data retention errors are rare during this period. The other solution is to employ data scrubbing that periodically refreshes data by reading and then writing the data to new locations after correcting errors through ECC. Though it is a viable solution for the retention error problem, data scrubbing hurts performance and lifetime of SSDs as it incurs extra read and write requests. Targeting data retention errors, we propose incremental redundancy (IR) that incrementally reinforces error correction capabilities when the data retention error rate exceeds a certain threshold. This extends the time before data scrubbing should occur, providing a grace period in which the block may be garbage collected. We develop mathematical analyses that project the lifetime and performance of IR as well as when using conventional data scrubbing. Through mathematical analyses and experiments with both synthetic and real workloads, we compare the lifetime and performance of the two schemes. Results suggest that IR can be a promising solution to overcome data retention errors of contemporary multi-bit cell flash memory. In particular, our study shows that IR can extend the maximum data retention period by 5 to 10 times. Additionally, we show that IR can reduce the write amplification factor by half under real workloads.

Original languageEnglish
Title of host publication31st Symposium on Massive Storage Systems and Technologies, MSST 2015
PublisherIEEE Computer Society
ISBN (Electronic)9781467376198
DOIs
StatePublished - 17 Aug 2015
Event31st Symposium on Massive Storage Systems and Technologies, MSST 2015 - Santa Clara, United States
Duration: 30 May 20155 Jun 2015

Publication series

NameIEEE Symposium on Mass Storage Systems and Technologies
Volume2015-August
ISSN (Print)2160-1968

Conference

Conference31st Symposium on Massive Storage Systems and Technologies, MSST 2015
Country/TerritoryUnited States
CitySanta Clara
Period30/05/155/06/15

Keywords

  • Ash
  • Bit error rate
  • Error correction codes
  • Mathematical analysis
  • Redundancy

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