Independent double-gate fin SONOS flash memory fabricated with sidewall spacer patterning

Jang Gn Yun; Yoon Kim; II Han Park; Jung Hoon Lee; Daewoong Kang; Myoungrack Lee; Hyungcheol Shin; Jong Duk Lee; Byung Gook Park

doi:10.1109/TED.2009.2024228

Independent double-gate fin SONOS flash memory fabricated with sidewall spacer patterning

Jang Gn Yun, Yoon Kim, II Han Park, Jung Hoon Lee, Daewoong Kang, Myoungrack Lee, Hyungcheol Shin, Jong Duk Lee, Byung Gook Park

School of Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

16 Scopus citations

Abstract

Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) Flash memories having independent double gates are fabricated and characterized. This device has two sidewall gates sharing one Si fin. To achieve narrow Si fin width over the photolithography limitation, sidewall spacer patterning is adopted. Specific fabrication processes for the fin SONOS Flash memory having independent double gates are described. Electrical properties related to the opposite gate dependence are characterized. Measurement results of the paired cell interference are delivered.

Original language	English
Pages (from-to)	1721-1728
Number of pages	8
Journal	IEEE Transactions on Electron Devices
Volume	56
Issue number	8
DOIs	https://doi.org/10.1109/TED.2009.2024228
State	Published - 2009

Keywords

Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) Flash memory
Interference coupling
Paired cell interference (PCI)
Separated double gates
Sidewall spacer patterning

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10.1109/TED.2009.2024228

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title = "Independent double-gate fin SONOS flash memory fabricated with sidewall spacer patterning",

abstract = "Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) Flash memories having independent double gates are fabricated and characterized. This device has two sidewall gates sharing one Si fin. To achieve narrow Si fin width over the photolithography limitation, sidewall spacer patterning is adopted. Specific fabrication processes for the fin SONOS Flash memory having independent double gates are described. Electrical properties related to the opposite gate dependence are characterized. Measurement results of the paired cell interference are delivered.",

keywords = "Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) Flash memory, Interference coupling, Paired cell interference (PCI), Separated double gates, Sidewall spacer patterning",

author = "Yun, {Jang Gn} and Yoon Kim and Park, {II Han} and Lee, {Jung Hoon} and Daewoong Kang and Myoungrack Lee and Hyungcheol Shin and Lee, {Jong Duk} and Park, {Byung Gook}",

year = "2009",

doi = "10.1109/TED.2009.2024228",

language = "English",

volume = "56",

pages = "1721--1728",

journal = "IEEE Transactions on Electron Devices",

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T1 - Independent double-gate fin SONOS flash memory fabricated with sidewall spacer patterning

AU - Yun, Jang Gn

AU - Kim, Yoon

AU - Park, II Han

AU - Lee, Jung Hoon

AU - Kang, Daewoong

AU - Lee, Myoungrack

AU - Shin, Hyungcheol

AU - Lee, Jong Duk

AU - Park, Byung Gook

PY - 2009

Y1 - 2009

N2 - Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) Flash memories having independent double gates are fabricated and characterized. This device has two sidewall gates sharing one Si fin. To achieve narrow Si fin width over the photolithography limitation, sidewall spacer patterning is adopted. Specific fabrication processes for the fin SONOS Flash memory having independent double gates are described. Electrical properties related to the opposite gate dependence are characterized. Measurement results of the paired cell interference are delivered.

AB - Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) Flash memories having independent double gates are fabricated and characterized. This device has two sidewall gates sharing one Si fin. To achieve narrow Si fin width over the photolithography limitation, sidewall spacer patterning is adopted. Specific fabrication processes for the fin SONOS Flash memory having independent double gates are described. Electrical properties related to the opposite gate dependence are characterized. Measurement results of the paired cell interference are delivered.

KW - Fin silicon-oxide-nitride-oxide-semiconductor (SONOS) Flash memory

KW - Interference coupling

KW - Paired cell interference (PCI)

KW - Separated double gates

KW - Sidewall spacer patterning

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M3 - Article

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SN - 0018-9383

VL - 56

SP - 1721

EP - 1728

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 8

ER -

Independent double-gate fin SONOS flash memory fabricated with sidewall spacer patterning

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Keywords

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