Inter-deck-body Architecture to Enhance Erase Speed in 3D NAND Flash Memory

In this study, we propose a novel Inter-Deck-Body (IDB) architecture to enhance the erase operation performance of 3D NAND flash memory. The IDB architecture is positioned between adjacent decks and consists of a P⁺ IDB region, an N⁺ channel connector, and four IDB dummy cells. During the erase operation, holes are directly supplied from the P⁺ IDB region to the channel, thereby boosting the channel potential. Unlike conventional 3D NAND flash memories that rely on gate-induced drain leakage (GIDL) for erase operation, the proposed architecture achieves erase without inducing GIDL current. Technology computer-aided design (TCAD) simulations were conducted to verify the functionality of the proposed IDB structure. Through these simulations, optimal structural parameters and biasing conditions for each operation mode were identified. In particular, it was demonstrated that the IDB-based erase scheme exhibits superior erase efficiency compared to conventional GIDL-based erase methods. Moreover, the proposed architecture ensures read operation without degradation in on-current, maintaining high read performance. These results indicate that the proposed IDB architecture is a highly scalable and promising solution for multi-deck 3D NAND flash memory, offering both improved erase performance and read integrity.