@inproceedings{54a29edd2d6743a9845ab6d206dd949c,
title = "Investigation into the effect of the variation of gate dimensions on program characteristics in 3D NAND flash array",
abstract = "In 3D stacked NAND flash memory, the number of stacked layers tends to increase for high density storage capacity. With the increase of the height of devices, it is important to achieve a good vertical etch profile by which word line (WL) gate dimensions are affected. In this paper, we investigate the effect of the variation of gate dimensions on the program characteristics in 3D NAND flash memory array by using TCAD simulation. Also, we compare the cell characteristics of NAND flash with different structures, gate-all-around (GAA) and double gate (DG).",
keywords = "3D stacked NAND flash",
author = "Seo, {Joo Yun} and Yoon Kim and Park, {Se Hwan} and Wandong Kim and Kim, {Do Bin} and Lee, {Jong Ho} and Hyungcheol Shin and Park, {Byung Gook}",
year = "2012",
doi = "10.1109/SNW.2012.6243320",
language = "English",
isbn = "9781467309943",
series = "2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012",
booktitle = "2012 IEEE Silicon Nanoelectronics Workshop, SNW 2012",
note = "2012 17th IEEE Silicon Nanoelectronics Workshop, SNW 2012 ; Conference date: 10-06-2012 Through 11-06-2012",
}