Line edge roughness and process variation effect of three stacked gate-all-around silicon MOSFET devices

In this paper, characteristics of line edge roughness (LER) and process variation effect (PVE) were investigated for a three stacked gate-all-around (GAA) nanowire (NW) field effect transistor (FET) through 3-D technology computer-aided design (TCAD) simulations. The stacked device has robust immunity for GAA LER as well as high driving current in comparison with single NW FET. On the other hand, the stacked device has PVE, which causes the difference of channel thickness on each stack. Particularly, the channel of the bottom region has larger channel radius than that of the other stacks. As the disparity of each stack becomes larger, the driving currents are concentrated on the bottom channel, which leads to high stress such as hot carrier degradation on the bottom channel.