Low power size-efficient CMOS UWB low-noise amplifier design

Hee Sayk Jhon; Ickhyun Song; Jongwook Jeon; Min Suk Koo; Byung Gook Park; Jong Duk Lee; Hyungcheol Shin

doi:10.1002/mop.24104

Low power size-efficient CMOS UWB low-noise amplifier design

Hee Sayk Jhon, Ickhyun Song, Jongwook Jeon, Min Suk Koo, Byung Gook Park, Jong Duk Lee, Hyungcheol Shin

School of Advanced Fusion Studies

Seoul National University

Research output: Contribution to journal › Article › peer-review

Abstract

The design and measurement results of 3-5 GHz fully integrated ultra-wideband (UWB) CMOS LNA are presented. To boost the trans conductance of the LNA and to reduce circuit area effectively, we eliminate a source degeneration inductor using resistive-feedback cascade structure. The implemented UWB LNA shows peak gain of 10.8 dB, more than 10 dB of input return loss, and a noise figure of 33-4.2 dB from 3 to 5.1 GHz with power dissipation of 14 mW. The input PldB and input IP3 (IIP3) at 4 GHz are about -6 dBm and +4 dBm, respectively. For low cost, the LNA has been fabricated using a 0.18-μm thin metal CMOS process with top metal thickness of 0.84 μm.

Original language	English
Pages (from-to)	494-496
Number of pages	3
Journal	Microwave and Optical Technology Letters
Volume	51
Issue number	2
DOIs	https://doi.org/10.1002/mop.24104
State	Published - Feb 2009

Keywords

CMOS
Low noise amplifier (LNA)
Mixedsignal
Ultra-wide band (UWB)

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10.1002/mop.24104

Cite this

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title = "Low power size-efficient CMOS UWB low-noise amplifier design",

abstract = "The design and measurement results of 3-5 GHz fully integrated ultra-wideband (UWB) CMOS LNA are presented. To boost the trans conductance of the LNA and to reduce circuit area effectively, we eliminate a source degeneration inductor using resistive-feedback cascade structure. The implemented UWB LNA shows peak gain of 10.8 dB, more than 10 dB of input return loss, and a noise figure of 33-4.2 dB from 3 to 5.1 GHz with power dissipation of 14 mW. The input PldB and input IP3 (IIP3) at 4 GHz are about -6 dBm and +4 dBm, respectively. For low cost, the LNA has been fabricated using a 0.18-μm thin metal CMOS process with top metal thickness of 0.84 μm.",

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AU - Jhon, Hee Sayk

AU - Song, Ickhyun

AU - Jeon, Jongwook

AU - Koo, Min Suk

AU - Park, Byung Gook

AU - Lee, Jong Duk

AU - Shin, Hyungcheol

PY - 2009/2

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AB - The design and measurement results of 3-5 GHz fully integrated ultra-wideband (UWB) CMOS LNA are presented. To boost the trans conductance of the LNA and to reduce circuit area effectively, we eliminate a source degeneration inductor using resistive-feedback cascade structure. The implemented UWB LNA shows peak gain of 10.8 dB, more than 10 dB of input return loss, and a noise figure of 33-4.2 dB from 3 to 5.1 GHz with power dissipation of 14 mW. The input PldB and input IP3 (IIP3) at 4 GHz are about -6 dBm and +4 dBm, respectively. For low cost, the LNA has been fabricated using a 0.18-μm thin metal CMOS process with top metal thickness of 0.84 μm.

KW - CMOS

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KW - Ultra-wide band (UWB)

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Low power size-efficient CMOS UWB low-noise amplifier design

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Keywords

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