Low temperature characterization of PMOS-type gate-all-around silicon nanowire FETs as single-hole-transistors

B. H. Hong, S. W. Hwang, Y. Y. Lee, M. H. Son, D. Ahn, K. H. Cho, K. H. Yeo, D. W. Kim, G. Y. Jin, D. Park

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

We report the single hole tunneling characteristics observed from a PMOS-type gate-all-around silicon nanowire field-effect-transistor with the radius 5 nm and the length 44 nm. The total capacitance of the quantum dot obtained from the measured Coulomb oscillations and Coulomb diamonds matches with the ideal capacitance of the silicon cylinder. It suggests that the observed single hole tunneling is originated from the fabricated structure.

Original languageEnglish
Title of host publicationPhysics of Semiconductors - 30th International Conference on the Physics of Semiconductors, ICPS-30
Pages291-292
Number of pages2
DOIs
StatePublished - 2011
Event30th International Conference on the Physics of Semiconductors, ICPS-30 - Seoul, Korea, Republic of
Duration: 25 Jul 201030 Jul 2010

Publication series

NameAIP Conference Proceedings
Volume1399
ISSN (Print)0094-243X
ISSN (Electronic)1551-7616

Conference

Conference30th International Conference on the Physics of Semiconductors, ICPS-30
Country/TerritoryKorea, Republic of
CitySeoul
Period25/07/1030/07/10

Keywords

  • Gate all around
  • Silicon nanowire field effect transistor
  • Temperature dependence

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