Low-voltage operating solution-processed CdS thin-film transistor with Ca ₂ Nb ₃ O ₁₀ nanosheets deposited using Langmuir–Blodgett method for a gate insulator

One of the most demanding challenges in next-generation thin-film transistors (TFTs) is the development of new materials for high-performance devices with higher speed and lower operation voltage. To drive a TFT at a low power, it is important to form an insulating layer as a thin film with good characteristics. Langmuir–Blodgett (LB) technique is one of the most suitable methods for controlling and developing two-dimensional nanomaterials. In the LB method, a layer only one molecule thick (Langmuir monolayer) is spread at the air/water interface and transferred onto the surface of a solid substrate and the process can be repeated several times with the same substrate to deposit multilayer films. In this study, a Ca ₂ Nb ₃ O ₁₀ (CNO) dielectric layer was fabricated using the LB method, and a CdS active layer was fabricated using the chemical bath deposition (CBD) method to obtain the final structure of CdS-TFTs. CNO dielectric layers have low leakage current density (7.26 × 10 ⁻⁷ A cm ⁻² ) and a high capacitance density of 944 nF cm ⁻² at 100 kHz. Therefore, it is considered that the CNO films produced using the LB method are suitable as an insulating layer material. Furthermore, the CdS-TFTs exhibited good performance with a low threshold voltage of 0.596 V, I _on /I _off current ratio of 10 ⁶ , subthreshold slope of 0.05 V dec ⁻¹ , and high mobility of 0.428 cm ² V ⁻¹ s ⁻¹ at operating voltages less than 2 V.