TY - GEN
T1 - Modeling of Charge Loss Mechanisms during the Short Term Retention Operation in 3-D NAND Flash Memories
AU - Woo, Changbeom
AU - Lee, Myeongwon
AU - Kim, Shinkeun
AU - Park, Jaeyeol
AU - Choi, Gil Bok
AU - Seo, Moon Sik
AU - Noh, Keum Hwan
AU - Kang, Myounggon
AU - Shin, Hyungcheol
N1 - Publisher Copyright:
© 2019 The Japan Society of Applied Physics.
PY - 2019/6
Y1 - 2019/6
N2 - Right after program, stored electrons in the shallow nitride trap level can be released less than a few seconds. By setting the delay between program and reading phase to as small as 10μs, we found that several mechanisms are mixed when stored electrons are emitted during short term retention of 3-D NAND Flash. For the first time, we have confirmed that the charge loss mechanisms consist of three mechanisms and have separated each mechanism. In particular, the vertical redistribution of electrons in the charge trap layer, observed only during short term, was analyzed for the first time. Short term retention data measured at various temperatures (25-115°C) and at several program verify levels (PV3, PV5, PV7) in solid (S/P) and checker-board patterns (C/P) were analyzed using our model. Finally, the activation energy (Ea) of each mechanism was extracted by the Arrhenius law and the magnitudes of Ea were compared.
AB - Right after program, stored electrons in the shallow nitride trap level can be released less than a few seconds. By setting the delay between program and reading phase to as small as 10μs, we found that several mechanisms are mixed when stored electrons are emitted during short term retention of 3-D NAND Flash. For the first time, we have confirmed that the charge loss mechanisms consist of three mechanisms and have separated each mechanism. In particular, the vertical redistribution of electrons in the charge trap layer, observed only during short term, was analyzed for the first time. Short term retention data measured at various temperatures (25-115°C) and at several program verify levels (PV3, PV5, PV7) in solid (S/P) and checker-board patterns (C/P) were analyzed using our model. Finally, the activation energy (Ea) of each mechanism was extracted by the Arrhenius law and the magnitudes of Ea were compared.
UR - http://www.scopus.com/inward/record.url?scp=85070301568&partnerID=8YFLogxK
U2 - 10.23919/VLSIT.2019.8776579
DO - 10.23919/VLSIT.2019.8776579
M3 - Conference contribution
AN - SCOPUS:85070301568
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - T214-T215
BT - 2019 Symposium on VLSI Technology, VLSI Technology 2019 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 39th Symposium on VLSI Technology, VLSI Technology 2019
Y2 - 9 June 2019 through 14 June 2019
ER -