New process of electroplate Sn bumping on TSV without a PR mould for 3D-chip stacking

Jiheon Jun, Inrak Kim, Jaepil Jung, Y. Norman Zhou

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


A new method of fabricating Sn bumps by electroplating without a PR (photoresist) mould on a Si die was investigated in terms of the bump growth and morphology for application to 3D-chip stacking. The omission of the PR mould was expected to result in a reduction of the process time and of the cost of electroplate bumping on the Si chip. For the electroplating of Sn bumps, a cathode consisting of a Si die with a Cuplugged TSV (through-silicon via) was used, with Sn or Pt adopted as an anode. The current densities and plating times were varied to assess the change in the Sn bump size and morphology. As a result, Sn bumps with rivet-head shapes were successfully fabricated via electroplating on Cu-plugged TSV without a PR mould. The height and width of the Sn bump were increased at a longer plating time and a larger current density. The Sn or Pt anode had a minimal effect on the electroplating results: The deposition rates and morphologies of the Sn bumps with different anodes were nearly identical in the range from 15 to 60 min at-30 mA/cm2. The Sn deposit without a PR mould developed a facet with various directions less than 5 min of plating time. After 15 min, however, the selective growth of some facets became dominant, which enlarged the preferred facets and caused a decrease in the number of facets.

Original languageEnglish
Pages (from-to)631-635
Number of pages5
JournalMetals and Materials International
Issue number4
StatePublished - Aug 2011


  • Sn bump
  • electrochemistry
  • electronic materials
  • plating
  • scanning electron microscopy (SEM)


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