New program inhibition scheme for high boosting efficiency in three-dimensional NAND array

In this work, program inhibition in a three-dimensional (3D) NAND array has been studied by technology computer-aided design (TCAD) simulation. Results indicate a variation in boosting efficiency among unselected channels with respect to their bias conditions. This variation can cause severe program disturbance in a NAND array. To reduce this potential variation, a new method that guarantees a reliable program inhibition has been designed. With this new scheme, the unwanted threshold voltage (VTH) shift of unselected cells induced by program disturbance can be notably reduced.