NOR-Type 3-D Synapse Array Architecture Based on Charge-Trap Flash Memory

Jung Nam Kim, Jaehong Lee, Jo Eun Kim, Suck Won Hong, Minsuk Koo, Yoon Kim

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


In this work, we proposed a three-dimensional (3-D) channel stacked array architecture based on charge-trap flash (CTF) memory for an artificial neural network accelerator. The proposed synapse array architecture could be a promising solution for implementing efficiently a large-size artificial neural network on a limited-size hardware chip. We designed a full array architecture including a stacked layer selection circuit. In addition, we investigated the synaptic characteristics of CTF device by using technology computer-aided design (TCAD) simulation. We demonstrated the feasibility of the synapse array for neural network accelerators through a system-level MATLAB simulation with the Modified National Institute of Standards and Technology (MNIST) database.

Original languageEnglish
Pages (from-to)813-820
Number of pages8
JournalIEEE Journal of the Electron Devices Society
StatePublished - 2022


  • 3-D stacked synapse array
  • CTF memory
  • artificial neural network
  • neuromorphic system
  • synapse array
  • synapse device


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