Abstract
In this work, we proposed a three-dimensional (3-D) channel stacked array architecture based on charge-trap flash (CTF) memory for an artificial neural network accelerator. The proposed synapse array architecture could be a promising solution for implementing efficiently a large-size artificial neural network on a limited-size hardware chip. We designed a full array architecture including a stacked layer selection circuit. In addition, we investigated the synaptic characteristics of CTF device by using technology computer-aided design (TCAD) simulation. We demonstrated the feasibility of the synapse array for neural network accelerators through a system-level MATLAB simulation with the Modified National Institute of Standards and Technology (MNIST) database.
Original language | English |
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Pages (from-to) | 813-820 |
Number of pages | 8 |
Journal | IEEE Journal of the Electron Devices Society |
Volume | 10 |
DOIs | |
State | Published - 2022 |
Keywords
- 3-D stacked synapse array
- CTF memory
- artificial neural network
- neuromorphic system
- synapse array
- synapse device