Novel three dimensional (3D) NAND flash memory array having tied bit-line and ground select transistor (TiGer)

Se Hwan Park; Yoon Kim; Wandong Kim; Joo Yun Seo; Hyungjin Kim; Byung Gook Park

doi:10.1587/transele.E95.C.837

Novel three dimensional (3D) NAND flash memory array having tied bit-line and ground select transistor (TiGer)

Se Hwan Park, Yoon Kim, Wandong Kim, Joo Yun Seo, Hyungjin Kim, Byung Gook Park

School of Electrical and Computer Engineering

Seoul National University

Research output: Contribution to journal › Article › peer-review

1 Scopus citations

Abstract

We propose a new three-dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) [1]. Channels are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked channels, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed.

Original language	English
Pages (from-to)	837-841
Number of pages	5
Journal	IEICE Transactions on Electronics
Volume	E95-C
Issue number	5
DOIs	https://doi.org/10.1587/transele.E95.C.837
State	Published - May 2012

Keywords

3 dimensional NAND flash memory
Operation scheme
Program inhibition

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10.1587/transele.E95.C.837

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AU - Kim, Hyungjin

AU - Park, Byung Gook

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Novel three dimensional (3D) NAND flash memory array having tied bit-line and ground select transistor (TiGer)

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Keywords

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