Optimization of Stacked Nanoplate FET for 3-nm Node

Hyunsuk Kim; Dokyun Son; Ilho Myeong; Jaeyeol Park; Myounggon Kang; Jongwook Jeon; Hyungcheol Shin

doi:10.1109/TED.2020.2976041

Optimization of Stacked Nanoplate FET for 3-nm Node

Hyunsuk Kim, Dokyun Son, Ilho Myeong, Jaeyeol Park, Myounggon Kang, Jongwook Jeon, Hyungcheol Shin

School of Advanced Fusion Studies

Research output: Contribution to journal › Article › peer-review

11 Scopus citations

Abstract

In this article, various characteristics of nanoplate FET were studied based on TCAD simulation for a 3-nm node. The optimum geometry specification was proposed through comparison of RC delay from previous studies. Additionally, the impacts of self-heating effects (SHEs) in the 3-nm node were evaluated in the targeting device because it is expected that highly scaled areas such as channels have a negative effect on the performance due to low heat dissipation. This degradation was verified in a single device and in ring oscillator (RO) operation. pMOS is comparatively stronger than nMOS in terms of SHEs due to wider channel width. In RO operation, the influence of SHEs begins to appear at over 0.65 V through power and speed comparison. Therefore, an operation voltage under 0.65 V can be the optimal voltage to suppress SHEs.

Original language	English
Article number	9031739
Pages (from-to)	1537-1541
Number of pages	5
Journal	IEEE Transactions on Electron Devices
Volume	67
Issue number	4
DOIs	https://doi.org/10.1109/TED.2020.2976041
State	Published - 1 Apr 2020

Keywords

FinFET
Nanoplate FET
Self-heating effects (SHEs)

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10.1109/TED.2020.2976041

Cite this

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abstract = "In this article, various characteristics of nanoplate FET were studied based on TCAD simulation for a 3-nm node. The optimum geometry specification was proposed through comparison of RC delay from previous studies. Additionally, the impacts of self-heating effects (SHEs) in the 3-nm node were evaluated in the targeting device because it is expected that highly scaled areas such as channels have a negative effect on the performance due to low heat dissipation. This degradation was verified in a single device and in ring oscillator (RO) operation. pMOS is comparatively stronger than nMOS in terms of SHEs due to wider channel width. In RO operation, the influence of SHEs begins to appear at over 0.65 V through power and speed comparison. Therefore, an operation voltage under 0.65 V can be the optimal voltage to suppress SHEs.",

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AU - Kang, Myounggon

AU - Jeon, Jongwook

AU - Shin, Hyungcheol

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AB - In this article, various characteristics of nanoplate FET were studied based on TCAD simulation for a 3-nm node. The optimum geometry specification was proposed through comparison of RC delay from previous studies. Additionally, the impacts of self-heating effects (SHEs) in the 3-nm node were evaluated in the targeting device because it is expected that highly scaled areas such as channels have a negative effect on the performance due to low heat dissipation. This degradation was verified in a single device and in ring oscillator (RO) operation. pMOS is comparatively stronger than nMOS in terms of SHEs due to wider channel width. In RO operation, the influence of SHEs begins to appear at over 0.65 V through power and speed comparison. Therefore, an operation voltage under 0.65 V can be the optimal voltage to suppress SHEs.

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Optimization of Stacked Nanoplate FET for 3-nm Node

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Keywords

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