Physics-Based Compact Model of Current Stress-Induced Threshold Voltage Shift in Top-Gate Self-Aligned Amorphous InGaZnO Thin-Film Transistors

Tae Jun Yang, Jingyu Park, Sungju Choi, Changwook Kim, Moonsup Han, Jong Ho Bae, Sung Jin Choi, Dong Myong Kim, Hong Jae Shin, Yun Sik Jeong, Jong Uk Bae, Chang Ho Oh, Dong Wook Park, Dae Hwan Kim

Research output: Contribution to journalArticlepeer-review

6 Scopus citations

Abstract

Threshold voltage shift ( Δ V T) under various current stress (CS) conditions need to be quantitatively studied in self-aligned top-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Here, we propose a stretched-exponential function (SEF)-based Δ V T model that can be applied to various combinations of V GS and VDS. The proposed model indicates the characteristic electron trapping time constant τ 1 is inversely proportional to (VGS - V T ). In contrast, the time constant τ 2 is directly proportional to the square root of ( VDS+Vbi), presumably due to the local donor creation by a lateral electric field. The proposed model was verified experimentally in various VGS and VDS configurations. Further, it is confirmed that the lateral electric field dominantly influences donor creation near the drain.

Original languageEnglish
Pages (from-to)1685-1688
Number of pages4
JournalIEEE Electron Device Letters
Volume43
Issue number10
DOIs
StatePublished - 1 Oct 2022

Keywords

  • InGaZnO thin-film transistors
  • current stress
  • donor creation
  • electron trapping
  • self-aligned top-gate structure

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