Physics-Based Compact Model of Current Stress-Induced Threshold Voltage Shift in Top-Gate Self-Aligned Amorphous InGaZnO Thin-Film Transistors

Threshold voltage shift ( Δ V T) under various current stress (CS) conditions need to be quantitatively studied in self-aligned top-gate amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs). Here, we propose a stretched-exponential function (SEF)-based Δ V T model that can be applied to various combinations of V GS and VDS. The proposed model indicates the characteristic electron trapping time constant τ 1 is inversely proportional to (VGS - V T ). In contrast, the time constant τ 2 is directly proportional to the square root of ( VDS+Vbi), presumably due to the local donor creation by a lateral electric field. The proposed model was verified experimentally in various VGS and VDS configurations. Further, it is confirmed that the lateral electric field dominantly influences donor creation near the drain.